1. Field of the Invention
This invention relates to computer circuits and, more particularly, to apparatus for eliminating bus contention at high clock frequencies in circuitry transferring digital data.
2. History of the Prior Art
In a typical computer circuit, a number of components are able to furnish data to a bus. All of these components are connected to the bus through individual switching circuits which allow the components to transfer data to and from the bus. The individual components each signal that they have information to be transferred on the bus, an arbitration operation determines which data is to go first, and the component with that data is connected to the bus through its switching circuitry so that it may transfer its data.
One problem that must be overcome is the tendency of different component circuits to want to drive the bus at the same time. Apart from any other problems, if two different components attempt to drive the bus at the same time, the data provided will almost certainly be incorrect for any purpose. The typical switching circuit which connects a component to a bus includes an output driver which is enabled to transfer data to the bus and turns off in order to release the bus for use by another component. When the bus is released by a component, the bus charges to a condition determined by a voltage (e.g., Vcc) applied through a pull up resistor. The switching circuit is not able to turn on or off instantaneously, and the time to turn on or off varies from device to device. A clock cycle is, therefore, often inserted after one device relinquishes the bus before another device may drive the bus to allow sufficient time for the bus to change state and avoid contention problems due to differences in switching speed. However, during this added cycle the bus is in an unknown state. This is an unacceptable solution in situations in which the system logic needs to drive the bus very rapidly.